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Modeling, Synthesis, and Rapid Prototyping with the VERILOG (TM) HDL
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Author: Michael D. Ciletti
List Price: $113.00
Our Price: Click to see the latest and low price
ISBN: 0139773983
Publisher: Prentice Hall (08 March, 1999)
Edition: Hardcover
Sales Rank: 276,659
Average Customer Rating: 3.12 out of 5
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Customer ReviewsRating: 4 out of 5
Recommended.
I am using this book for an introductory Verilog class at my University and I must say I am truely confused by some of the reviews here. Although this book takes the reader through the most basic elements of the Verilog language, to its more complex and esoteric uses, most people here complain that the it fails to provide the advanced, cutting-edge examples they feel it should have. What? Do you really expect to learn how to build a Pentium IV from a book teaching the basics of Verilog? Get real!This book teaches the basics, it teaches you how to use the Verilog language by providing examples that, although dated, illustrate timeless approaches that are used in every Verilog design large or small. If you can't find how to complement a variable, then its your fault, not the book; I can assure you its there. Furthermore, if you think that pointing out a few mistakes in the book, (and have obviously learnt the correct way of doing it from it), makes it rubbish, then I'm afraid there won't be any books that will fully satisfy your needs. This is one of the best books I've encountered on the Verilog langauge. Although I wouldn't say it's as good as, say, Ashendens VHDL, it is _not_ as bad as some of the reviews here make out. Recommended!
Rating: 2 out of 5
Writing is far from refined
The writing is fragmented and incomplete statements are often seen, for example:1. in section 4.6.4, it is written
"If A and B are vectors, A&&B returns true if both words are
positive integers." then no words there to specify "otherwise" part. If you assume otherwise A&&B returns false, you are wrong,
since A&&B returns true when both are negative integers too. 2. In 7.5.1, it says "There are two forms for delay control,...
The first form is ...", but the second form is never explained or mentioned there. 3. You often see
always @ ( a or b ) in examples with "or" in boldface,
but I could not find where "or" is defined. Even though I
understand its meaning, I wish to tell the differece from
using "|" , "||" 4. ... plus many typos These cause a lot confusion in reading
Rating: 4 out of 5
One of the best
This book is one best to learn Verilog with. Each chapter starts with an statement of the chapters objectives, then covers the topic with many examples and finally summarizes the chapter at the end. There are an series of questions at the end of each chapter that help to solidify the concepts within each chapter. (but no answers in the book). All in all I think that this is the best overall presentation of Verilog that I have read yet. Samir Palnitar's Verilog HDL is slower paced and thus better for the novice (I read this one first). This book is slightly more advanced and seems to take you further.
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